1. Field of the Invention
The present invention relates to a level shifter of a semiconductor device and, more particularly, to a level shifter of a semiconductor device capable of shifting the level of an output signal while precisely controlling a duty ratio of the output signal in a high-speed semiconductor device having operating performance that is sensitive even to slight distortion of the signal, and a method for controlling a duty ratio in the semiconductor device.
2. Description of Related Art
A power supply voltage keeps dropping with the rapid development of fine processing techniques. In order to meet the required specifications of high-speed systems such as high-speed digital communication systems, high-definition high-speed display devices, and mass storage devices, analog and digital blocks of the high-speed systems have been increasingly employing a plurality of power supply voltages. However, some semiconductor devices or some circuits for semiconductor devices require high voltages for operating characteristics. Therefore, when semiconductor devices or internal circuits thereof need high operating voltages, a voltage interface, for example, a level shifter, is required.
Meanwhile, two signals applied to an input terminal of a level shifter are delayed by different times and different times are taken to output a high-potential signal and a low-potential signal.
Meanwhile, two signals are input with different delay times to an input terminal of a level shifter, and high- and low-potential signals are output with different delay times from the level shifter. In other words, shifting the level of any signal changes a duty ratio of the signal, i.e., a ratio of a high-level duration to one signal cycle, resulting in an output signal with the duty cycle changed.
The duty ratio of the level shifter is critical in supplying a sampled clock signal to an analog block, such as an analog-to-digital converter (ADC). The performance of a clock-based analog block greatly depends on the duty ratio of an input clock. Therefore, due to a change in the duty ratio, the level shifter might not be applicable to high-speed semiconductor devices.
FIG. 1 is a circuit diagram of a conventional level shifter of a semiconductor device.
Referring to FIG. 1, the level shifter includes four NMOS transistors N1 to N4, two PMOS transistors P1 and P2, and an inverter INV.
A power supply voltage LS_P is applied in common to sources of the first and second PMOS transistors P1 and P2 and gates of the first and third NMOS transistors N1 and N3. A series connection of the first and second NMOS transistors N1 and N2 with one side grounded is connected to a drain of the first PMOS transistor P1. Also, a series connection of the third and fourth NMOS transistors N3 and N4 with one side grounded is connected to a drain of the second PMOS transistor P2.
An input signal VIN is applied to a gate of the second NMOS transistor N2. The input signal VIN is inverted by the inverter INV so that an inverted input signal VINB is applied to a gate of the fourth NMOS transistor N4. A gate of the first PMOS transistor P1 is connected to the drain of the second PMOS transistor P2 to form a second output terminal LS_OUT2. Also, a gate of the second PMOS transistor P2 is connected to the drain of the first PMOS transistor P1 to form a first output terminal LS_OUT1.
The operation of the conventional level shifter of the semiconductor device shown in FIG. 1 will now be described.
First, since the power supply voltage LS_P is applied in common to the gates of the first and third NMOS transistors N1 and N3, the first and third NMOS transistors N1 and N3 are turned on.
When the input signal VIN is at a low level, the second NMOS transistor N2 is turned off, and the fourth NMOS transistor N4 is turned on. Accordingly, since a voltage of a node T2 is at the level of a ground voltage Vss, the first PMOS transistor P1 is turned on. Then, since a voltage of a node T1 becomes at the level of the power supply voltage LS_P, the second PMOS transistor P2 is turned on. Since the voltage of the node T1 is at the level of the power supply voltage LS_P, the level of the power supply voltage LS_P is output from the first output terminal LS_OUT1. Also, since the voltage of the node T2 is at the level of the ground voltage Vss, the level of the ground voltage Vss is output from the second output terminal LS_OUT2.
When the input signal VIN is at a high level, the second NMOS transistor N2 is turned on, and the fourth NMOS transistor N4 is turned off. Accordingly, since the voltage of the node T1 is at the level of the ground voltage Vss, the second PMOS transistor P2 is turned on. Then, since the voltage of the node T2 becomes at the level of the power supply voltage LS_P, the first PMOS transistor P1 is turned off. Since the voltage of the node T1 is at the level of the ground voltage Vss, the level of the ground voltage Vss is output from the first output terminal LS_OUT1. Also, since the voltage of the node T2 is at the level of the power supply voltage LS_P, the level of the power supply voltage LS_P is output from the second output terminal LS_OUT2.
FIG. 2 is a timing diagram illustrating the operation of the conventional level shifter of the semiconductor device shown in FIG. 1. In FIG. 2, VIN denotes an input signal, VINB denotes an inverted input signal, LS_OUT1 denotes a negative output signal of the level shifter, and LS_OUT2 denotes appositive output signal of the level shifter.
The input signal VIN toggles between a low level and a high level in a predetermined bit cycle. The bit cycle includes a high bit cycle Tb in which the input signal VIN makes a low-to-high transition, remains at a high level, and drops to a low level, and a low bit cycle Td in which the input signal VIN makes a high-to-low transition, remains at a low level, and rises to a high level.
The inverted input signal VINB is obtained by inverting the input signal VIN using the inverter INV. The inverted input signal VINB is delayed by an inverter delay time Td_inv later than the input signal VIN.
The positive output signal LS_OUT2 makes a transition to the level of a power supply voltage LS_P, which is delivered after a predetermined rising delay time Td_r via the second PMOS transistor P2 that is turned on in response to the input signal VIN, makes a transition to the level of a ground voltage Vss, which is delivered via the fourth NMOS transistor N4 that is turned on in response to the inverted input signal VINB, and is output.
The negative output signal LS_OUT1 makes a transition to the level of the ground voltage Vss, which is delivered via the second NMOS transistor N2 that is turned on in response to the input signal VIN, makes a transition to the level of the power supply voltage LS_P, which is delivered after a predetermined rising delay time Td_r via the first PMOS transistor P1 that is turned on in response to the inverted input signal VINB, and is output.
In this case, when neglecting the delay time Td_inv of the inverter INV, the output signals LS_OUT1 and LS_OUT2 of the level shifter have rising delay times that are longer than falling delay times. This is due the fact that the output signals LS_OUT1 and LS_OUT2 fall directly after the inverted input signal VINB rises to a high level and the fourth NMOS transistor N4 is turned on, while the output signals LS_OUT1 and LS_OUT2 of the level shifter do not rise until the input signal VIN rises to a high level, the inverted input signal VINB drops to a low level, and the second PMOS transistor P2 transmits the power supply voltage LS_P.
The operation of the conventional level shifter of the semiconductor device will now be described with reference to FIGS. 1 and 2.
First, since the power supply voltage LS_P is applied in common to the gates of the first and third NMOS transistors N1 and N2 of the level shifter 12, the NMOS transistors N1 and N2 are turned on.
When the input signal VIN makes a low-to-high transition at a point in time t1, the second NMOS transistor N2 is turned on and thus, the level of the ground voltage Vss is delivered to the node T1 and a voltage level of the first output terminal LS_OUT1 directly drops to the level of the ground voltage Vss.
When the level of the ground voltage Vss of the node T1 is applied to the gate of the second PMOS transistor P2, the second PMOS transistor P2 is turned on. Thus, the level of the power supply voltage LS_P of the second output terminal LS_OUT2 is delayed by a predetermined rising delay time Td_r and delivered to the node T2, so that the positive output signal LS_OUT2 makes a transition to the level of the power supply voltage LS_P at a point in time t2 after the rising delay time Td_r.
Thereafter, when the input signal VIN makes a high-to-low transition at a point in time t3, a high-level voltage is applied via the inverter INV to the gate of the fourth NMOS transistor N4. Thus, the fourth NMOS transistor N4 is turned on and the level of the ground voltage Vss is delivered to the node T2, so that a voltage level of the second output terminal LS_OUT2 drops to the level of the ground voltage Vss at a point in time t4 after an inverter delay time Td_inv.
When the level of the ground voltage Vss of the node T2 is applied to the gate of the first PMOS transistor P1, the first PMOS transistor P1 is turned on. Thus, the level of the power supply voltage LS_P of the first output terminal LS_OUT1 is delayed by a predetermined rising delay time Td_rb and delivered to the node T1, so that the negative output signal LS_OUT1 makes a transition to the level of the power supply voltage LS_P at a point in time t5 after the rising delay time Td_rb.
In general, the level shifter receives the input signal VIN and generates the positive output signal LS_OUT2 and the negative output signal LS_OUT1. However, because the level shifter outputs only one output signal LS_OUT2 and uses the other output signal LS_OUT1 to shift the voltage level of the input signal VIN, the duty ratios of the output signals LS_OUT1 and LS_OUT2 can be different.
Accordingly, since a ratio of a high bit cycle of an output signal to the entire bit cycle of the output signal is defined as a duty ratio of the output signal, the duty ratio of the positive output signal LS_OUT2, which is used as a substantial output signal of the level shifter, should be ½, i.e., 50%, while the duty ratio of the negative output signal LS_OUT1, which is used to shift the level of the input signal VIN, may not be 50%.
Referring to FIG. 2, a high bit cycle and a low bit cycle of the input signal VIN correspond to the original high bit cycle Tb and the original low bit cycle Td, respectively. However, a high bit cycle of the positive output signal LS_OUT2 is given by subtracting the rising delay time Td_r of the positive output signal LS_OUT2 from the sum of the current high bit cycle Tb and the inverter delay time Td_inv, and a low bit cycle of the positive output signal LS_OUT2 is given by taking the sum of the rising delay time Td_r of the positive output signal LS_OUT2 and a time given by subtracting the inverter delay time Td_inv from the current high bit cycle Tb.
Therefore, the entire bit cycle of the positive output signal LS_OUT2 becomes 2Tb and the high bit cycle of the positive output signal LS_OUT2 becomes Tb+Td_inv-Td_r, so that the duty ratio of the positive output signal LS_OUT2 may not exactly be 50%.
In the conventional art as described above, the inverted input signal VINB is delayed by a predetermined delay time due to the inverter INV and drops to a low level later than the input signal VIN. Thus, problems caused when a rising delay time Td_r of the output signal LS_OUT2 of the level shifter is longer than a falling delay time thereof can be reduced. However, in the semiconductor device having operating performance that is sensitive even to slight distortion of an output waveform, it is difficult to precisely control the duty ratio of the output signal LS_OUT2 by using the inverter INV that greatly varies a delay time and a duty ratio according to the size of a transistor.